Autor: |
Tomoyuki Ishii, Tokuo Kure, T. Sano, Fumio Murai, Kazuo Yano, Toshiyuki Mine, Takayuki Hashimoto, T. Kobayashi, Koichi Seki |
Rok vydání: |
1999 |
Předmět: |
|
Zdroj: |
Proceedings of the IEEE. 87:633-651 |
ISSN: |
0018-9219 |
DOI: |
10.1109/5.752519 |
Popis: |
Starting with a brief review on the single-electron memory and its significance among various single-electron devices, this paper addresses the key issues which one inevitably encounters when one tries to achieve giga-to-tera bit memory integration. Among the issues discussed are: room-temperature operation; memory-cell architecture; sensing scheme; cell-design guideline; use of nanocrystalline silicon versus lithography; array architecture; device-to-device variations; read/write error rate; and CMOS/single-electron-memory hybrid integration and its positioning among various memory architectures. |
Databáze: |
OpenAIRE |
Externí odkaz: |
|