A Highly Punchthrough-Immune Array Architecture and Program Method for Floating-Gate NOR-Type Nonvolatile Memory

Autor:	Tien Fan Ou, C. C. Cheng, Wen-Jer Tsai, Kuang-Chao Chen, C M Yih, T K Chu, Chun-Yuan Lu, Ping Hung Tsai, J.S. Huang, S G Yan, C.H. Cheng, Tao Cheng Lu, Chih-Yuan Lu, C S Hung
Rok vydání:	2011
Předmět:	Non-volatile memory business.industry Cascade Computer science Logic gate Electrical engineering Node (circuits) Electrical and Electronic Engineering business Electronic Optical and Magnetic Materials
Zdroj:	IEEE Transactions on Electron Devices. 58:945-952
ISSN:	1557-9646 0018-9383
Popis:	A novel array architecture is proposed for floating-gate nor-type nonvolatile memory cells. By embedding a floating n+ region between two cells in each memory pair, punchthrough (PT) immunity is greatly improved. Since the operating cell and the cascade cell belong to two independent word-lines, bit-pattern effect on read and program characteristics is mitigated, and multilevel-cell storage can be easily realized. No additional program disturb has been found. Erase, endurance, and retention characteristics are comparable with its conventional counterpart. According to simulations, Lg as short as 56 nm, which is projected to serve for 28 nm technology node, is feasible without suffering a serious PT effect.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::64385ed837cbffacd2ef4faee00e088d https://doi.org/10.1109/ted.2011.2104960 Zobrazit plný text záznamu