Autor: |
Anne Vandooren, E. Vecchio, Niamh Waldron, Geert Hellings, W. Li, Nadine Collaert, Lan Peng, Eddy Kunnen, Liesbeth Witters, Fumihiro Inoue, Dan Mocuta |
Rok vydání: |
2017 |
Předmět: |
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Zdroj: |
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). |
Popis: |
We are proposing a double gate junction-less device with a processing temperature compatible with state-of-the-art dense low k dielectric back-end of line copper process. The thermal stability of the back-end of line process was studied, showing no degradation for an anneal temperature up to 500°C 1h. Using wafer bonding, a crystalline silicon layer can be transferred onto a carrier wafer followed by top device processing at low temperature with a gate first approach as well as direct W contacts with Ti/TiN barrier layer. To avoid dopant activation using high temperature anneal (spike), junction-less devices are used, where the uniform channel dopant implantation and activation can be done prior to the layer transfer. |
Databáze: |
OpenAIRE |
Externí odkaz: |
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