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Design rules for the next generation of VLSI and ULSI devices will routinely require the plasma etching of sub-micron geometries. These requirements will create even greater challenges for the exposure and devolopment of photoresist on reflective and severe topographies. Two processes developed to meet these challenges are Multi-Level Resist processing and the Dry Development of Photoresist. Critical to both of these processes is the need for a productive, >4000A/min, anisotropic etch of photoresist with critical dimension loss of |
