3D embedded wafer-level packaging technology development for smart card SIP application

Autor: J. Noiray, J. Mazuir, C. Bouvier, M. Saadaoui, A. Planchais, G. Simon, G. Pares, K. Martinschitz
Rok vydání: 2012
Předmět:
Zdroj: 2012 IEEE 14th Electronics Packaging Technology Conference (EPTC).
DOI: 10.1109/eptc.2012.6507097
Popis: Fan-Out wafer level packaging (eWLP) has been proven to be a valuable solution for producing compact multi-die packages with high performances and is from now on in volume production[1–3]. Known good dies are rebuilt in a molding compound matrix wafer and fan out redistribution layer and bumps are subsequently built on top of the as-formed strata. In this work we present a novel ultra-thin 3D-eWLP technology designed for smart-card products integrating heterogeneous ICs in a three stacked strata architecture.
Databáze: OpenAIRE