Background Calibration With Piecewise Linearized Error Model for CMOS Pipeline A/D Converter

Autor:	Jie Yuan, J. Van der Spiegel, Nabil H. Farhat
Rok vydání:	2008
Předmět:	Spurious-free dynamic range Dynamic range Calibration (statistics) Computer science Pipeline (computing) Analog-to-digital converter law.invention CMOS law Control theory Hardware_INTEGRATEDCIRCUITS Piecewise Electrical and Electronic Engineering Error detection and correction
Zdroj:	IEEE Transactions on Circuits and Systems I: Regular Papers. 55:311-321
ISSN:	1558-0806 1549-8328
DOI:	10.1109/tcsi.2007.910645
Popis:	A new all-digital background calibration method, using a piecewise linear model to estimate the stage error pattern, is presented. The method corrects both linear and nonlinear errors. The proposed procedure converges in a few milliseconds and requires low hardware overhead, without the need of a high-capacity ROM or RAM. The calibration procedure is tested on a 0.6-mum CMOS pipeline analog-to-digital converter (ADC), which suffers from a high degree of nonlinear errors. The calibration gives improvements of 17 and 26 dB for signal-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR), respectively, for the Nyquist input signal at the sampling rate of 33 MSample/s. The calibrated ADC achieves SNDR of 70.3 dB and SFDR of 81.3 dB at 33 MSample/s, which results in a resolution of about 12 b.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::6396177e8bf2c18305e79da517e68fec https://doi.org/10.1109/tcsi.2007.910645 Zobrazit plný text záznamu