Investigation of stepwise charging circuits for power-clock generation in Adiabatic Logic
| Autor: | Himadri Singh Raghav, Izzet Kale, Vivian A. Bartlett |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Adiabatic circuit
Energy recovery Engineering business.industry 020208 electrical & electronic engineering Electrical engineering Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Integrated circuit Capacitance 020202 computer hardware & architecture Power (physics) law.invention law Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering business Adiabatic process Science technology and society Electronic circuit |
| Zdroj: | 2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME). |
| Popis: | The generation of power-clocks in adiabatic integrated circuits is investigated. Specifically, we consider stepwise charging strategies (2, 3, 4, 5, 6, 7, and 8-step) based on tank-capacitor circuits, comparing them in terms of their energy recovery properties and complexity. We show that energy recovery achievable depends on the tank-capacitor size. We also show that tank-capacitor sizes can be reduced as their number increases concluding that combined tank capacitance (CTT) versus load capacitance (CL) ratio is the significant parameter. We propose that using a CTT/CL ratio of 10 and using a 4-step charging power-clock constitute appropriate trade-offs in practical circuits. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|