| Popis: |
In this paper, we propose a new division circuit for applications. The proposed division circuit is based on a modified the binary GCD algorithm and produce division results at a rate of one per 2m-1 clock cycles. Analysis shows that the proposed circuit gives and improvements in terms of speed and hardware respectively. In addition, since the proposed circuit does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and scalability with respect to the field size m. Thus, the proposed divider. is well suited to low-area applications. |
