Autor: |
JuneYoung Park, SukHwan Jang, Dojin Park, Ji-Hoon Jung, JinKyung Kim, Sung-Kyu Jung, Kang-Yoon Lee, YoungGun Pu |
Rok vydání: |
2006 |
Předmět: |
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Zdroj: |
2006 Proceedings of the 32nd European Solid-State Circuits Conference. |
DOI: |
10.1109/esscir.2006.307539 |
Popis: |
This paper presents a fast switching CMOS frequency synthesizer with a new coarse tuning method for PHS applications. To achieve the fast lock-time and the low phase noise performance, an efficient bandwidth control scheme is proposed. Charge pump up/down current mismatches are compensated with the current mismatch compensation block. Also, the proposed coarse tuning method selects the optimal tuning capacitances of the LC-VCO to optimize the phase noise and the lock-time. The measured lock-time is about 20 mus and the phase noise is - 121dBc/radicHz at 600kHz offset. This chip is fabricated with 0.25mum CMOS technology, and the die area is 0.7mm times 2.1mm. The power consumption is 54mW at 2.7V supply voltage |
Databáze: |
OpenAIRE |
Externí odkaz: |
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