| Autor: |
Jonathan Cobb, Amy Yang, Yunqiang Zhang, Ji Li, Kevin Lucas, Satyendra Sethi |
| Rok vydání: |
2008 |
| Předmět: |
|
| Zdroj: |
Photomask Technology 2008. |
| ISSN: |
0277-786X |
| DOI: |
10.1117/12.801593 |
| Popis: |
Semiconductor manufacturers spend hundreds of millions of dollars and years of development time to create a new manufacturing process and to design frontrunner products to work on the new process. A considerable percentage of this large investment is aimed at producing the process design rules and related lithography technology to pattern the new products successfully. Significant additional cost and time is needed in both process and design development if the design rules or lithography strategy must be modified. Therefore, early and accurate prediction of both process design rules and lithography options is necessary for minimizing cost and timing in semiconductor development. This paper describes a methodology to determine the optimum design rules and lithography conditions with high accuracy early in the development lifecycle. We present results from the 32nm logic node but the methodology can be extended to the 22nm node or any other node. This work involves: automated generation of extended realistic logic test layouts utilizing programmed teststructures for a variety of design rules; determining a range of optical illumination and process conditions to test for each critical design layer; using these illumination conditions to create a extrapolatable process window OPC model which is matched to rigorous TCAD lithography focus-exposure full chemically amplified resist models; creating reticle enhancement technique (RET) recipes which are flexible enough to be used over a variety of design rule and illumination conditions; OPC recipes which are flexible enough to be used over a variety of design rule and illumination conditions; and OPC verification to find, categorize and report all patterning issues found in the different design and illumination variations. In this work we describe in detail the individual steps in the methodology, and provide results of its use for 32nm node design rule and process optimization. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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