Choice of power-supply voltage for half-micrometer and lower submicrometer CMOS devices
| Autor: | M. Kinugawa, M. Kakumu, Kazuhiko Hashimoto |
|---|---|
| Rok vydání: | 1990 |
| Předmět: |
Engineering
Voltage reduction business.industry Electrical engineering Hardware_PERFORMANCEANDRELIABILITY Integrated circuit Circuit reliability Electronic Optical and Magnetic Materials law.invention Reliability (semiconductor) CMOS law Gate oxide Hardware_INTEGRATEDCIRCUITS Electrical and Electronic Engineering business AND gate Hardware_LOGICDESIGN Voltage |
| Zdroj: | IEEE Transactions on Electron Devices. 37:1334-1342 |
| ISSN: | 0018-9383 |
| DOI: | 10.1109/16.108196 |
| Popis: | The tradeoff between circuit performance and reliability is theoretically and experimentally examined in detail, down to half-micrometer and lower submicrometer gate lengths, taking into account high-field effects on MOSFETs. Some guidelines for optimum power-supply voltage and process/device parameters for half-micrometer and lower submicrometer CMOS devices are proposed in order to maintain MOS device reliability and achieve high circuit performance. It is shown that power-supply voltage must be reduced to maintain reliability and improved performance and that the optimum voltage reduction follows the square root of the design rule. Trends for scaling down power-supply voltage have been experimentally verified by results obtained from measurements on CMOS devices over a wide range of gate oxide thickness (7-45 nm) and gate lengths (0.3-2.0 mu m). > |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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