TCAD analysis of FinFET stress engineering for CMOS technology scaling

Autor:	Amaury Gendron-Hansen, Konstantin Korablev, Francis Benistant, Jin Cho, James Egley, Ivan Chakarov
Rok vydání:	2015
Předmět:	Stress (mechanics) Cmos technology scaling CMOS Computer science Logic gate Stress engineering Electronic engineering Semiconductor device Scale down High stress
Zdroj:	2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).
DOI:	10.1109/sispad.2015.7292349
Popis:	In this paper, we analyze the mechanical stress induced from source/drain embedded SiGe (eSiGe) in multiple generations of FinFET technologies. By leveraging TCAD simulations, we show that high stress over the entire fin height could be achieved with a proper design of the eSiGe cavity. We also find that the stress should not undergo any reduction as the industry continues to scale down CMOS technologies. Hence, it should still play a major role in boosting semiconductor device performance for the next generation of FinFETs.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::620fe3f41e69a211141c98fdcb798d61 https://doi.org/10.1109/sispad.2015.7292349 Zobrazit plný text záznamu