A Fully Pipelined Hardware Architecture for Intra Prediction of HEVC
| Autor: | Ray C. C. Cheung, Biao Min, Zhe Xu |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
Hardware architecture
Pixel business.industry Computer science Real-time computing 02 engineering and technology Display resolution 020202 computer hardware & architecture 0202 electrical engineering electronic engineering information engineering Media Technology 020201 artificial intelligence & image processing Electrical and Electronic Engineering business Computer hardware Decoding methods |
| Zdroj: | IEEE Transactions on Circuits and Systems for Video Technology. 27:2702-2713 |
| ISSN: | 1558-2205 1051-8215 |
| DOI: | 10.1109/tcsvt.2016.2593618 |
| Popis: | Ultrahigh definition (UHD), such as 4K/8K, is becoming the mainstream of video resolution nowadays. High Efficiency Video Coding (HEVC) is the emerging video coding standard to process the encoding and decoding of UHD video. This paper first develops multiple techniques that allow the proposed hardware architecture for intra prediction of HEVC working in full pipeline. The proposed techniques include: 1) a novel buffer structure for reference samples; 2) a mode-dependent scanning order; and 3) an inverse method for reference sample extension. The size of the buffer is 3K b for luma component and 3K b for chroma components, providing sufficient accessing to the reference samples. Since the data dependency between two neighboring blocks is addressed by the mode-dependent scanning order, the proposed fully pipelined design can produce 4 pixels/clock cycle. As a result, the throughput of the proposed architecture is capable to support $3840 \times 2160$ videos at 30 frames/s. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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