Hardware Accelerator for Dual Standard Deblocking Filter
| Autor: | B. Syndia Priyadarshini, P. Saravanan, P. Vignesh Kanna, P. Vaishnavi |
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| Rok vydání: | 2021 |
| Předmět: |
Deblocking filter
Computer science business.industry Macroblock 020206 networking & telecommunications Image processing 02 engineering and technology Video quality Parallel processing (DSP implementation) 0202 electrical engineering electronic engineering information engineering Hardware acceleration 020201 artificial intelligence & image processing business Field-programmable gate array Throughput (business) Computer hardware |
| Zdroj: | VLSI Design |
| Popis: | Advanced Video Coding (AVC) also known as H.264 is a popular video coding standard which is used in many image processing applications. In order to fulfill the increasing demand for better video quality with less complex designs, High Efficiency Video Coding (HEVC) also known as H.265 came into picture. HEVC provides better quality with half the bit rate required for processing in comparison with AVC. In case of AVC, the design of deblocking filter is more complex due to the filtering decisions, whereas HEVC is less complex and also supports parallel processing. As there is a need for high throughput and less complex deblocking filter, a novel dual standard deblocking filter is proposed in this work which supports both AVC and HEVC. In particular, a novel filtering order which enables four edges to be processed simultaneously has been proposed for both AVC and HEVC. For AVC, the proposed design takes 18 clock cycles to process a 16 × 16 macroblock and for HEVC standard, the proposed design takes 12 clock cycles to process a 16 × 16 coding transform unit (CTU). In addition to this, the proposed design supports parallel processing concept in HEVC. The proposed design is synthesized using Xilinx ISE 14.7 and is mapped to xc5vlx30-1ff324 Virtex-5 Field programmable gate array (FPGA). Thus it helps in increasing the execution speed of the design and it is also noted that there is a reduction in number of clock cycles needed for processing when compared with the existing architectures. The physical implementation of the proposed architecture is also carried out using Semiconductor Lab (SCL) 180 nm process node. |
| Databáze: | OpenAIRE |
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