A Novel Reconfigurable Sensing Scheme for Variable Level Storage in Phase Change Memory

Autor: Matthew J. Breitwisch, Tien-Yen Wang, Richard C. Jordan, Roger W. Cheek, Thomas M. Maffitt, Jackie Morrish, Hsiang-Lan Lung, Chung H. Lam, Alejandro G. Schrott, Scott C. Lewis, Jing Li, Chao-I Wu
Rok vydání: 2011
Předmět:
Zdroj: 2011 3rd IEEE International Memory Workshop (IMW).
Popis: This paper presents a novel reconfigurable sensing scheme with the flexibility to change reading precision of analog resistance levels for MLC PCM. A 2Mcell PCM chip was fabricated in 90nm CMOS technology and was tested. Operating at 8-bits precision (adequate for 7b/cell PCM i.e., 128 resistance levels), read access latency is 5μs (measured at 50MHz clock), compared to 35-50μs in state-of-art 2b/cell NAND Flash.
Databáze: OpenAIRE