An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch
| Autor: | Alexander Petrie, Mau-Chung Frank Chang, Yong Qu, Hunter Jensen, Eric Swindlehurst, Jieh-Tsorng Wu, Yixin Song, Yen-Cheng Kuan, Shiuh-hua Wood Chiang |
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| Rok vydání: | 2021 |
| Předmět: |
Spurious-free dynamic range
Computer science Dynamic range 8-bit Successive approximation ADC Hardware_PERFORMANCEANDRELIABILITY law.invention Capacitor Parasitic capacitance Sampling (signal processing) law Hardware_INTEGRATEDCIRCUITS Electronic engineering Redundancy (engineering) Electrical and Electronic Engineering |
| Zdroj: | IEEE Journal of Solid-State Circuits. 56:2347-2359 |
| ISSN: | 1558-173X 0018-9200 |
| Popis: | An 8-bit 10-GHz 8 $\times $ time-interleaved successive-approximation-register (SAR) analog-to-digital converter (ADC) incorporates an aggressively scaled digital-to-analog converter (DAC) with grouped capacitors in a symmetrical structure to afford a threefold reduction in the bottom-plate parasitic capacitance. A detailed study rigorously analyzes the effect of gradient on the proposed DAC layout. The DAC additionally implements quantized sub-radix-2 scaling with redistributed redundancy. A high-speed dual-path bootstrapped switch decouples the critical signal from the nonlinear parasitic capacitance to boost the sampling spurious-free dynamic range (SFDR) by more than 5 dB. Fabricated in a 28-nm CMOS process, the ADC demonstrates an SNDR of 36.9 dB at Nyquist while consuming 21 mW, yielding a figure-of-merit of 37 fJ/conv.-step, the best among state-of-the-arts. |
| Databáze: | OpenAIRE |
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