Reducing FPGA algorithm area by avoiding redundant computation

Autor:	Michel Laverne, Brian Axelrod
Rok vydání:	2015
Předmět:	Kernel (image processing) Computer science Computation Corner detection Algorithm design Parallel computing Frame rate Field-programmable gate array Implementation Algorithm
Zdroj:	ICRA
DOI:	10.1109/icra.2015.7139226
Popis:	We develop a new paradigm for designing fully streaming, area-efficient FPGA implementations of common building blocks for vision algorithm. By focusing on avoiding redundant computation we achieve a reduction of one to two orders of magnitude reduction in design area utilization as compared to previous implementations. We demonstrate that our design works in practice by building five 325 frames per second, high resolution Harris corner detection cores onto a single FPGA.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::6054b25d58bb48317e47dc0f0e084736 https://doi.org/10.1109/icra.2015.7139226 Zobrazit plný text záznamu