A Hybrid Divide—16 Frequency Divider Design for Low Power Phase Locked Loop Design

Autor:	Jayachandra Prasad Talari, Venkateswarlu Surisetty, Ravi Nirlakalla, Supraja Batchu
Rok vydání:	2015
Předmět:	Phase-locked loop Frequency divider Computer science Power consumption business.industry Electrical engineering Wilkinson power divider business Current divider Hybrid model Power (physics)
Zdroj:	Proceedings of the International Conference on Soft Computing Systems ISBN: 9788132226697
DOI:	10.1007/978-81-322-2671-0_47
Popis:	In this paper, we present a divide by 16 frequency divider (FD) for high frequency and low power phase locked loop (PLL) designs. The FDs have shown efficiency in different parameters. Divide by 16 FDs are proposed with a hybrid model which combined with a true single-phase clock (TSPC) and E-TSPC for low power PLL. Results of FDH1 have shown low power consumption.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::604bf3d0c021dac7fa8fd84247b5df64 https://doi.org/10.1007/978-81-322-2671-0_47 Zobrazit plný text záznamu