Differential current-mode clock distribution

Autor:	Matthew R. Guthaus, Riadul Islam, Hany A. Fahmy, Ping-Yao Lin
Rok vydání:	2015
Předmět:	Physics Synchronous circuit Clock domain crossing Clock signal Clock rate Electronic engineering Clock gating Digital clock manager Hardware_LOGICDESIGN Clock network CPU multiplier
Zdroj:	MWSCAS
DOI:	10.1109/mwscas.2015.7282042
Popis:	In this paper, we present a differential current-mode pulsed flip-flop (DCMPFF) for low-power clock distribution using a representative 45nm CMOS technology. Experimental results show that the DCMPFF has 47% faster clock-to-output (CLK-Q) delay than a traditional voltage-mode (VM) pulsed flip-flop. When the DCMPFF is integrated with a differential current-mode clock distribution, the differential technique saves 62% and 17% power compared to a conventional VM and a previous current-mode (CM) clock network, respectively.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::5fce0e51a469b8f41bff6b9a67872fc7 https://doi.org/10.1109/mwscas.2015.7282042 Zobrazit plný text záznamu