Systematic validation of 2x nm diameter perpendicular MTJ arrays and MgO barrier for sub-10 nm embedded STT-MRAM with practically unlimited endurance
| Autor: | Jaesoo Ahn, Jimmy Kan, Lin Xue, A. Kontos, Seung H. Kang, Mangesh Bangar, S. Kim, H. Chen, Chando Park, S. Hassan, Wang Rongjun, C. Ching, Liang Shurong, Mahendra Pakala |
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| Rok vydání: | 2016 |
| Předmět: |
010302 applied physics
Magnetoresistive random-access memory Materials science Dielectric strength business.industry Electrical engineering Time-dependent gate oxide breakdown 02 engineering and technology 01 natural sciences Temperature measurement 020202 computer hardware & architecture CMOS 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Perpendicular Breakdown voltage Optoelectronics business Voltage |
| Zdroj: | 2016 IEEE International Electron Devices Meeting (IEDM). |
| DOI: | 10.1109/iedm.2016.7838493 |
| Popis: | We present a comprehensive device and scalability validation of STT-MRAM for high performance applications in sub-10 nm CMOS by providing the first statistical account of barrier reliability in perpendicular magnetic tunnel junctions (pMTJs) from 70 to 25 nm diameter in 1 Gbit arrays. We have experimentally investigated the time-dependent dielectric breakdown (TDDB) properties and the dependence of the pMTJ lifetime on voltage, polarity, duty-cycle, and temperature. A large write-to-breakdown voltage window of > 1 V (> 20 σavg) was measured and a long time-to-breakdown was projected (> 1015 cycles) for 45 nm pMTJs, guaranteeing practically unlimited write cycles. We also reveal a dramatic enhancement of barrier reliability in conjunction with pMTJ size scaling down to 25 nm diameter, further widening the operating window at deeply scaled nodes. |
| Databáze: | OpenAIRE |
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