A Novel Implementation of RISI Controller Employing Adaptive Clock Gating Technique
| Autor: | M Kamaraju, Praveen V N Desu |
|---|---|
| Rok vydání: | 2011 |
| Předmět: |
General Computer Science
Interrupt latency business.industry Computer science Open-loop controller Keyboard controller Clock gating Advanced Programmable Interrupt Controller Programmable Interrupt Controller Instruction set Control theory Embedded system Verilog Central processing unit Interrupt business computer Interrupt request computer.programming_language |
| Zdroj: | International Journal of Advanced Computer Science and Applications. 2 |
| ISSN: | 2156-5570 2158-107X |
| DOI: | 10.14569/ijacsa.2011.021104 |
| Popis: | With the scaling of technology and the need for higher performance and more functionality power dissipation is becoming a major issue for controller design. Interrupt based programming is widely used for interfacing a processor with peripherals. The proposed architecture implements a mechanism which combines interrupt controller and RIS (Reduced Instruction Set) CPU (Central processing unit) on a single die. RISI Controller takes only one cycle for both interrupt request generation and acknowledgement. The architecture have a dynamic control unit which consists of a program flow controller, interrupt controller and I/O controller. Adaptive clock gating technique is used to reduce power consumption in the dynamic control unit. The controller consumes a power of 174µw@1MHz and is implemented in verilog HDL using Xilinx platform |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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