| Autor: |
Kuppili Sunil Kumar, R. V. Siva Krishna Addagattu, Kothapalli Roopa |
| Rok vydání: |
2020 |
| Předmět: |
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| Zdroj: |
Lecture Notes in Electrical Engineering ISBN: 9789811538278 |
| DOI: |
10.1007/978-981-15-3828-5_1 |
| Popis: |
This paper proposes a novel design which is capable of faster data recovery for high-speed communications such as serializer and deserializer (SerDes). The SerDes is an essential and widely used component in high-speed gigabit communications such as PCIe, Ethernet, passive optical networks (PON), MIPI and HD video streaming interfaces. The high-speed serializer/deserializer is the dominant implementation of I/O interfaces at speeds of 2.5 Gbps and higher. The SerDes works with a source-synchronous interface in which no synchronization clock will be present while transmitting/receiving the data. The SerDes receivers must have the clock and data recovery (CDR) circuit which dynamically extracts the clock and data from the receiving differential serial data. The design in this paper proposes a Nyquist sampling-based architecture that will simultaneously capture the serial data with high redundancy and without any bit loss. The architecture uses an algorithm which also features the adaptive sampling rate independent of the bit duration. The algorithm is capable of estimating the interleaving window between successive bits and significantly analyzes the samples of successive bits and dynamically filters the noisy samples and recovers the bit information and also has the ability to adjust the offset deviations occurred while sampling the serial data. The algorithm is implemented and verified on the SerDes serial receiver at 25 Gbps data rate at 14 nm technology node. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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