Heterogeneous Integration Using Organic Interposer Technology
| Autor: | KiYeul Yang, Nathan Whitchurch, Michael G. Kelly, Curtis Zwenger, George J. Scott, TaeKyeong Hwang, WonMyoung Ki, JongHyun Jeon, JaeHun Bae |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
010302 applied physics
Multi-core processor Silicon business.industry Computer science 020208 electrical & electronic engineering SerDes Electrical engineering chemistry.chemical_element Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Integrated circuit 01 natural sciences law.invention chemistry Application-specific integrated circuit law 0103 physical sciences Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Interposer Central processing unit Parasitic extraction business |
| Zdroj: | 2020 IEEE 70th Electronic Components and Technology Conference (ECTC). |
| DOI: | 10.1109/ectc32862.2020.00145 |
| Popis: | As the costs of advanced node silicon have risen sharply with the 7 and 5-nanometer nodes, advanced packaging is coming to a crossroad where it is no longer fiscally prudent to pack all desired functionality into a single die. While single-die packages will still be around, the high-end market is shifting towards multiple-die packages to reduce overall costs and improve functionality. This shift is not just to add local memory, such as the addition of high-bandwidth memory (HBM) module(s) to an application-specific integrated circuit (ASIC) die, but also to separate what would have been a monolithic ASIC in prior generations to its constituent parts, such as the central processing unit (CPU) cores, serializer/deserializer (SerDes) and input/output (I/O) blocks. By splitting the monolithic die into smaller functional blocks, costs can be reduced through improved wafer yield on the smaller CPU cores and re-using older, vetted intellectual property (IP) from a prior silicon node for the I/O and SerDes that do not necessarily need the most advanced silicon node.The traditional approach to fine-pitch multi-die packaging has been silicon interposers with Through Silicon Vias (TSVs). While the TSV approach has ushered in new performance levels never seen before, one of the major limitations is the inability to scale with higher and higher frequencies. The maximum frequency that a silicon interposer can handle between die-to-die interconnects is approximately 4 GHz due to the parasitics of the silicon. As dieto-die interconnects increase their bandwidth to higher and higher levels, the 4-6 GHz limitation can become a major bottleneck. Eliminating the silicon and silicon dioxide dielectrics and using polymers as the dielectric and the interposer itself can solve this problem.This paper will discuss how to use High-Density Fan-Out (HDFO) technology to replace the TSV-bearing silicon interposer with an organic interposer to enable higher bandwidth die-to-die interconnects for heterogeneous integration. |
| Databáze: | OpenAIRE |
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