Intelligent Optimization Approaches for a Secured Dynamic Partial Reconfigurable Architecture-Based Health Monitoring System

Autor: R. Saravana Ram, M. Lordwin Cecil Prabhaker
Rok vydání: 2022
Předmět:
Zdroj: Journal of Circuits, Systems and Computers. 32
ISSN: 1793-6454
0218-1266
Popis: In this work, an intelligent multi-objective optimization technique is proposed to optimize various parameters such as power consumption ([Formula: see text]), computation time ([Formula: see text]) and area ([Formula: see text]) for a health monitoring system designed using the Secured Dynamic Partial Reconfiguration (SDPR) architecture. The cost-efficient Dynamic Partial Reconfiguration (DPR)-based field-programmable gate array (FPGA) is very useful for analyzing many applications such as automation and data processing. The novelty of this paper is to design a new intelligent SDPR (i-SDPR) module in order to achieve better performance in a health monitoring system by considering various performance parameters. The SDPR architecture is incorporated with two reconfigurable modules such as Encrypt and Authenticate, which results in an increase in the core power consumption ([Formula: see text]), computation time ([Formula: see text]) and area ([Formula: see text]). So, to improve the performance of the SDPR-based health monitoring system, there is a necessity to optimize the performance parameters and it is achieved through intelligent multi-objective evolutionary (MOEA) techniques. The intelligent multi-objective evolutionary techniques such as Niched-Pareto Genetic Algorithm (NPGA), Pareto Archived Evolution Strategy (PAES) and Pareto Envelope-based Selection Algorithm (PESA) have been considered for better optimization in the performance parameters. For the study, the free-to-use MIMIC-III dataset is taken, which contains critically admitted various intensive care unit patient data. The dataset is processed through any one of the multi-objective evolutionary operators till satisfying the conditions and then forwarded to implementation. The proposed architecture has been implemented and tested using Cyclone[Formula: see text] V SX SoC Development Kit. The comparative analysis of various performance parameters was done for the proposed i-SDPR with the existing techniques such as the DPR and SDPR approach to show the improvement. The results declare that the proposed techniques obtain better performance compared to the existing techniques.
Databáze: OpenAIRE
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