A Fast Locking All Digital Delay Locked Loop with wide operating frequency ranged from 0.5 GHz to 1.8 GHz in 40nm Process

Autor:	Ko-Chi Kuo
Rok vydání:	2021
Předmět:	Computer science Electronic engineering Operating frequency Process (computing) Digital delay locked loop
Zdroj:	2021 18th International SoC Design Conference (ISOCC).
DOI:	10.1109/isocc53507.2021.9613874
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::5f6e9ecd571db52a2d12397f66b3f2b3 https://doi.org/10.1109/isocc53507.2021.9613874 Zobrazit plný text záznamu