Clock controller design in SuperSPARC II microprocessor

Autor:	K. Bhabuthmal, H. Hao
Rok vydání:	2002
Předmět:	Engineering business.industry Underclocking Clock drift Clock gating Digital clock manager Clock skew Clock domain crossing ComputerSystemsOrganization_MISCELLANEOUS Embedded system Master clock Hardware_ARITHMETICANDLOGICSTRUCTURES business Computer hardware CPU multiplier
Zdroj:	ICCD
DOI:	10.1109/iccd.1995.528800
Popis:	This paper describes the SuperSPARC II clock controller. This controller allows the internal clock to be disabled during the chip's normal operation. Then any number of internal clock pulses can be issued in a controlled fashion. The clock can return to the free running mode after being disabled. All clock control is done in a way that produces no glitches on the internal clock signal The clock controller can be accessed through the IEEE 1149.1 interface, making it useful at the chip level and at the module or system level.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::5f0bd4ed55d8132da629c57e0ccb1ac6 https://doi.org/10.1109/iccd.1995.528800 Zobrazit plný text záznamu