Design of power efficient stable 1-bit full adder circuit
| Autor: | Gajula Ramana Murthy, Ajay Kumar Singh, Shahmini Subramaniam |
|---|---|
| Rok vydání: | 2018 |
| Předmět: |
Adder
Pass transistor logic Computer science Monte Carlo method Power efficient 02 engineering and technology 021001 nanoscience & nanotechnology Condensed Matter Physics 020202 computer hardware & architecture Electronic Optical and Magnetic Materials Bit (horse) Reliability (semiconductor) Power consumption 0202 electrical engineering electronic engineering information engineering Electronic engineering Electrical and Electronic Engineering 0210 nano-technology Hardware_LOGICDESIGN |
| Zdroj: | IEICE Electronics Express. 15:20180552-20180552 |
| ISSN: | 1349-2543 |
| Popis: | This paper presents design of 14-T 1-bit full adder power efficient Pass Transistor Logic (PTL) based stable circuit. Due to compact architecture, power consumption is low and response is faster. MC (Monte Carlo) shows that the circuit is more reliable against any statistical variations |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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