Investigation of gate-bias stress and hot-carrier stress-induced instability of InGaZnO thin-film transistors under different environments
| Autor: | Chia-Sheng Lin, Yu-Te Chen, Jing-Yi Yan, Tien-Yu Hsieh, Wu-Wei Tsai, Ming-Yen Tsai, Ting-Chang Chang, Te-Chih Chen, Fu-Yen Jian, Wen-Jen Chiang |
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| Rok vydání: | 2013 |
| Předmět: |
Materials science
Passivation business.industry Electrical engineering Surfaces and Interfaces General Chemistry Condensed Matter Physics Capacitance Instability Surfaces Coatings and Films Active layer Threshold voltage Stress (mechanics) Thin-film transistor Materials Chemistry Density of states Optoelectronics business |
| Zdroj: | Surface and Coatings Technology. 231:478-481 |
| ISSN: | 0257-8972 |
| DOI: | 10.1016/j.surfcoat.2012.10.030 |
| Popis: | This paper investigates the temperature and ambiance effects on various reliability issues for InGaZnO thin film transistors with an organic passivation layer. Hot-carrier stress and gate-bias stress are carried out under different environmental temperatures and ambient gases. The device exhibits relatively good stability under room temperture, whereas high temperature enhances degradation. Futhermore, different degradation behaviors after gate-bias stress in atmosphere and in vacuum can be attributed to gas adsorption/desorption-induced instability. Moreover, capacitance-voltage measurement techinique is utilized to analyze the degradation mechanism and to extract the density of state (DOS). The result reveals that the threshold voltage shift after both hot-carrier and gate-bias stress originates from the charge-trapping effect at the interface of gate insulator and active layer, with the extra trap states generated during stress responsible for C-V curve distortion. In addition, the asymmetric degradation behavior of gate-to-drain capacitance (Cgd) and gate-to-source capacitance (Cgs) indicates that trap states are generated near the drain side. |
| Databáze: | OpenAIRE |
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