Simulation-based circuit-activity estimation for FPGAs containing hard blocks
| Autor: | Panagiotis Patros, Sean Seeley, Zack Deveau, Kenneth B. Kent, Vidya Sankaranaryanan |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
business.industry
Computer science CAD 02 engineering and technology computer.software_genre 020202 computer hardware & architecture Logic gate Black box Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Benchmark (computing) Computer Aided Design Electronics business Field-programmable gate array computer Computer hardware Hardware_LOGICDESIGN Electronic circuit |
| Zdroj: | RSP |
| DOI: | 10.1145/3130265.3130326 |
| Popis: | FPGAs are electronic devices that are programmable and can functionally perform equivalently to a number of other circuits. FPGAs are used for both rapid and cheap prototyping of new circuit designs as well as for replacing outdated chip models. Due to their complexity, circuits cannot be practically designed by hand; instead, specialized Computer Aided Design (CAD) software performs this complex task. A major concern for devices is power requirements, which can have adverse effects on both the environment and users. The power requirements of a circuit can be directly connected with its activity, which can be estimated by the CAD tools. In this work, we focus on the open source Verilog-To-Routing (VTR) CAD software and propose an improved activity estimation tool using VTR's synthesizer (Odin II) that extends beyond the capabilities of its current estimator (ACE2), such as proper black box activity propagation and support for circuits containing no clocks or more than one clock. Our results are experimentally evaluated with VTR's FPGA architectures and benchmark circuits. |
| Databáze: | OpenAIRE |
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