| Autor: |
Oliver D. Patterson, Camille Xu, Abdalmohsen Elmalk, Kuo-Feng Pao, Kunyuan Chen, Double Chung, Fuming Wang, Shane Su, Andy Lan, Sudharshanan Raghunathan, Marc Kea, Jason Liao, Daniels Bae, Aiqin Jiang, Richer Yang, Wallace He |
| Rok vydání: |
2021 |
| Předmět: |
|
| Zdroj: |
Metrology, Inspection, and Process Control for Semiconductor Manufacturing XXXV. |
| Popis: |
For advanced DRAM nodes, process window requirements have become extremely tight for Critical Dimension (CD) and Overlay. Determining process window based only on mean CD without quantifying defectivity on the wafer is no longer adequate. A superior approach illustrated in this paper is to generate pattern specific stochastic failure rate (FR) models that capture the non-normal nature of the fail rate distribution, using large numbers of measurements on focus-exposure-matrix (FEM) wafers. This model can be used to predict the FR contours to the part-per-billion (ppb) rate or more. The defectivity process window of course corresponds to the FR contour that meets the process FR requirement. Patterns can be grouped based on their characteristics into a single model, but generally multiple models must be generated to cover the range of printed geometries. This modeling methodology was applied to the periphery support circuitry for a DRAM technology currently in development. The particular layer involved bidirectional line/space pattern printed using DUV. Models were built and defectivity contour plots were generated for ten different patterns. Their contours at the target FR were compared with the purpose of determining if any posed a concern for high-volume manufacturing. Actually inspecting these patterns and directly measuring the FR to the PPB was impossible for two reasons: 1) The inspection time would be prohibitive 2) There are not enough replicates on the wafer to do this. To evaluate the accuracy of the final stochastic aware process windows, the FR on select patterns was directly measured and showed good agreement. This information can be used as a basis for modifying the OPC model or even the periphery design for problematic patterns. Overall this methodology provides a very efficient way to tune in patterning to meet HVM requirements. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
|
