A Current Estimation Method for Bias-Temperature Stress of a-Si TFT Device
| Autor: | Yeong-Shyang Lee, Ching-Chieh Shih, Feng-Yuan Gan, Kuo-Lung Fang, Ching-Hung Chen |
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| Rok vydání: | 2007 |
| Předmět: |
Amorphous silicon
Materials science business.industry Transistor Electronic Optical and Magnetic Materials law.invention Stress (mechanics) chemistry.chemical_compound Reliability (semiconductor) chemistry Thin-film transistor law Electronic engineering Optoelectronics Degradation (geology) Electrical and Electronic Engineering Current (fluid) Safety Risk Reliability and Quality business Voltage |
| Zdroj: | IEEE Transactions on Device and Materials Reliability. 7:347-350 |
| ISSN: | 1530-4388 |
| DOI: | 10.1109/tdmr.2007.901068 |
| Popis: | We have studied the time-dependence degradation of ON current of amorphous silicon thin-film transistors (a-Si:H TFTs), which is a function of stress duration, stress temperature, and stress bias. A simple method with stretched-exponential equation and current-voltage function is used to characterize and predict the TFT performance. Bias-temperature stress at different stress voltages has been performed on a-Si:H TFTs. A new method using ON current degradation to analyze TFT device performance is presented, which is different from the conventional threshold-voltage shift method. We have also observed that the beta value in the ON current degradation method compared to the threshold-voltage shift method, with a stretched-exponential stress time, is related to beta~beta0-TST/T0. Finally, we have also used the new equation to evaluate the performance of the gate-driver-on-array circuit in our products. If the limitation of the current for the pull-down device is 1times10-6 A, then the operation time of the pull-down device can be estimated to about 1219 h when key pulled-down TFT is operating at 60degC. |
| Databáze: | OpenAIRE |
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