Power Profiling of Modern Die-Stacked Memory
| Autor: | Yuan Xie, Amin Farmahini-Farahani, Michael Ignatowski, Dylan Stow, Sudhanva Gurumurthi |
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| Rok vydání: | 2019 |
| Předmět: |
Profiling (computer programming)
Hardware_MEMORYSTRUCTURES Computer science business.industry Interface (computing) 02 engineering and technology High Bandwidth Memory Power budget Bottleneck 020202 computer hardware & architecture Power (physics) Hardware and Architecture Embedded system 0202 electrical engineering electronic engineering information engineering Bandwidth (computing) business Dram |
| Zdroj: | IEEE Computer Architecture Letters. 18:132-135 |
| ISSN: | 2473-2575 1556-6056 |
| DOI: | 10.1109/lca.2019.2941715 |
| Popis: | Die-stacked memories that integrate multiple DRAM dies into the processor package have reduced the interface bottleneck and improved efficiency, but demands for memory capacity and bandwidth remain unfulfilled. Additionally, the introduction of memory into the package further complicates heat removal. Memory power is therefore becoming a key architectural concern. To provide insight into these challenges, an architectural power model for High Bandwidth Memory is developed, validated, and used to provide detailed power profiles. Based on the resulting power trends, power is projected for potential future memory configurations with increased bandwidth and capacity. The results suggest that, without significant improvements in memory technology or architecture, the power utilization of in-package memories will continue to grow and limit the system power budget. |
| Databáze: | OpenAIRE |
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