A low-leakage SCR design using trigger-PMOS modulations for ESD protection

Autor:	M. Okushima, Y. Morishita
Rok vydání:	2007
Předmět:	Electrostatic discharge Materials science CMOS business.industry Electrical engineering Thyristor Low leakage Integrated circuit design business Voltage PMOS logic
Zdroj:	2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).
DOI:	10.1109/eosesd.2007.4401776
Popis:	A low-leakage SCR design using trigger-PMOS modulations is proposed for ESD protection. By using the SCR design, a leakage current less than 10-13A was achieved together with a trigger voltage, VtI=1.8 V, and ESD performances 5.5 kV HBM and 300 V MM or over in our 65 nm CMOS technology. This design concept can be used for wide applications by changing the structure of the trigger-PMOS.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::5cc53c002d66b1798d908ce4db92b0d1 https://doi.org/10.1109/eosesd.2007.4401776 Zobrazit plný text záznamu