An integrated design environment of fault tolerant processors with flexible HW/SW solutions for versatile performance/cost/coverage tradeoffs
| Autor: | Jng-Jer Huang, Yi-Ju Ke, Yi-Chieh Ghen |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
Engineering
Integrated design Multi-core processor business.industry 020208 electrical & electronic engineering Fault tolerance 02 engineering and technology computer.software_genre 020202 computer hardware & architecture Embedded software Software Software fault tolerance Embedded system Fault coverage 0202 electrical engineering electronic engineering information engineering Operating system Redundancy (engineering) business computer |
| Zdroj: | ITC-Asia |
| DOI: | 10.1109/itc-asia.2017.8097134 |
| Popis: | This paper presents an integrated design environment (IDE) for embedded fault-tolerant processor system. It takes in a processor core IP and the embedded software which is to be executed on the given processor, and turns them into a fault-tolerant system with various hardware and software mechanisms, subject to the designer's selection. The hardware options include dual redundancy for processor core, and single-error-detection/correction protections for memory. The software option is control flow error detection. A GUI is provided for the designer to select the options and the IDE automatically generates the hardware Verilog code and the modified embedded software. The IDE reports the cost, speed and power consumption of the generated hardware and the static and dynamic instruction counts of the generated software. In addition, a fault-injection tool is also provided to evaluate the fault coverage of the generated hardware and software. With this IDE, the designer could explore the tradeoffs of cost/performance/ power/fault-coverage. We have successfully demonstrated this IDE with an industrial processor core Andes N8. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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