Design of Reliable SoCs With BIST Hardware and Machine Learning
| Autor: | Mark Tehranipoor, Jifeng Chen, Mehdi Sadi, Gustavo K. Contreras, LeRoy Winemberg |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
Engineering
Wear out business.industry Reliability (computer networking) 020208 electrical & electronic engineering 02 engineering and technology Machine learning computer.software_genre Field (computer science) 020202 computer hardware & architecture Set (abstract data type) Software Hardware and Architecture Embedded system 0202 electrical engineering electronic engineering information engineering Benchmark (computing) Time overhead Artificial intelligence Electrical and Electronic Engineering business computer Computer hardware |
| Zdroj: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25:3237-3250 |
| ISSN: | 1557-9999 1063-8210 |
| Popis: | In this paper, a novel framework is presented for designing lifetime-reliable SoCs with self-adaptation capability against aging-induced degradation. The proposed flow utilizes the existing logic built-in-self-test (LBIST) hardware, and software implemented machine learning predictor to activate appropriate countermeasures to remedy the wear out in the field. Using an innovative method, we convert ATPG-generated transition delay test patterns into LBIST patterns to activate high-usage critical/near-critical paths in-field, and the corresponding responses are utilized in developing the predictor. A gate-overlap and path-delay-aware algorithm selects the optimum set of patterns. The area and test time overhead for the framework are very low. We implemented our proposed flow on SoC benchmark designs, and the results demonstrated its efficacy. |
| Databáze: | OpenAIRE |
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