Hardware implementation of digital image skeletonization algorithm using FPGA for computer vision applications
| Autor: | Perumalla Srinivasa Rao, Kamatham Yedukondalu |
|---|---|
| Rok vydání: | 2019 |
| Předmět: |
business.industry
Computer science ComputingMethodologies_IMAGEPROCESSINGANDCOMPUTERVISION 020207 software engineering Image processing 02 engineering and technology Grayscale Reconfigurable computing Skeletonization Digital image Software Signal Processing Digital image processing 0202 electrical engineering electronic engineering information engineering Media Technology 020201 artificial intelligence & image processing Computer vision Computer Vision and Pattern Recognition Artificial intelligence Electrical and Electronic Engineering business Field-programmable gate array Algorithm Computer hardware |
| Zdroj: | Journal of Visual Communication and Image Representation. 59:140-149 |
| ISSN: | 1047-3203 |
| DOI: | 10.1016/j.jvcir.2019.01.004 |
| Popis: | Nowadays embedded multimedia devices are designed for computationally intensive applications such as image processing in various multimedia systems. Image processing algorithms should be implemented on hardware platforms for improving the performance. Reconfigurable hardware implementation using Field Programmable Gate Arrays (FPGAs) provides low latency with high performance in real time applications. FPGAs offer the reprogrammability of an application specific solution while retaining the performance advantage. In real time applications as image sizes increase rapidly, only hardware systems must be used with low complex software. In this paper, main perspective of developing and implementing skeletonization algorithm as a part of computer vision, pattern recognition application is focused and presented. A simple algorithm to skeletonize the 2-D image using MATLAB is developed. An architecture and implementation of this skeletonization algorithm for 2-D gray scale images is proposed. For analyzing pixel values 3 × 3 windowing operator is used. The proposed architecture is tested for an image size of 8 × 8, but the approach presented in this paper can be used for images of any size (M × N), if the FPGA memory is sufficiently large. The implementation was carried out on Xilinx Vertex 5 board. |
| Databáze: | OpenAIRE |
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