FPGA implementation of tunable arbitrary sequencer for key generation mechanism
| Autor: | Sanath Kumar Tulasi, M. Siva Kumar, B. Murali Krishna, K Hari Kishore, N Srinivasulu, N. Sai Tejeswi |
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| Rok vydání: | 2017 |
| Předmět: |
Key generation
Environmental Engineering Computer science business.industry 020209 energy General Chemical Engineering General Engineering 02 engineering and technology Hardware and Architecture Embedded system 0202 electrical engineering electronic engineering information engineering Computer Science (miscellaneous) Hardware_ARITHMETICANDLOGICSTRUCTURES Field-programmable gate array business Mechanism (sociology) Biotechnology |
| Zdroj: | International Journal of Engineering & Technology. 7:237 |
| ISSN: | 2227-524X |
| Popis: | In the present scenario information security has become a predominant issue. Cryptography is the process used for the purpose of information security. In cryptography message is encrypted with key produces cipher and decrypts the original message from cipher uses variety mechanisms and permutations. This paper presents a key generation mechanism suitable in cryptography applications which plays a vital role in data security. Random key generation techniques are multiplexed and configured in FPGA. In run time based on priority of section inputs randomly one method selectively produces a key which inputs to cryptosystem. Jitter process generates random numbers based on clock frequency triggered to oscillators, which produces pseudo random keys, but it consumes more resources when compared with other methods, but randomness in generated key is exponential. Pre stored random numbers in Block Memory are generated using IP core generator. The main advantage of the proposed model is to produce random keys which will be secure, predictable and attains high security. Due to its configurable nature, FPGA’s are suitable for wide variety of applications which can configure in runtime to implement custom designs and needs. Random number generation techniques are designed using Verilog HDL, simulated on Xilinx ISE simulator and implemented on Spartan FPGA. |
| Databáze: | OpenAIRE |
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