Minimizing inductive noise in system-on-a-chip with multiple power gating structures
| Autor: | David F. Heidel, Kevin Stawiasz, Daniel R. Knebel, Suhwan Kim, M. Immediato, Stephen V. Kosonocky |
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| Rok vydání: | 2004 |
| Předmět: |
Engineering
Power gating business.industry Electrical engineering Clock gating Hardware_PERFORMANCEANDRELIABILITY Power factor Noise generator Low-power electronics Hardware_INTEGRATEDCIRCUITS Electronic engineering Effective input noise temperature Power semiconductor device business Power network design Hardware_LOGICDESIGN |
| Zdroj: | ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705). |
| DOI: | 10.1109/esscirc.2003.1257215 |
| Popis: | A multiple power domain strategy in which each power domain has an independent power gating structure is an effective means for reducing leakage power consumption in a system-on-a-chip. During an individual power gating structure power-mode transition, however, serious inductive noise is introduced that may affect normal operation of neighboring circuits. We present a novel power gating structure in which inductive noise is reduced through gradual turn-on and turn-off its sleep transistor. Experimental simulation results with PowerSpice fixtured in different package models demonstrate the effectiveness of the proposed power gate switching noise reduction technique. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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