Design Space Exploration of a 512KB STT-Assisted SOT MRAM Cache
| Autor: | Marc Rosales, Jonathan Gabriel S.A. Reyes, Anastacia P. Ballesil-Alvarez, Christopher Santos, Maria Theresa de Leon, Maria Patricia Rouelli G. Sabino, Adrian G. Caburnay, John Richard E. Hizon |
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| Rok vydání: | 2020 |
| Předmět: |
010302 applied physics
Physics Magnetoresistive random-access memory Hardware_MEMORYSTRUCTURES Design space exploration business.industry Transistor Spin-transfer torque Electrical engineering 02 engineering and technology Energy consumption 01 natural sciences 020202 computer hardware & architecture law.invention law 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Torque Cache Latency (engineering) business |
| Zdroj: | ISOCC |
| DOI: | 10.1109/isocc50952.2020.9333087 |
| Popis: | The effects of varying the Spin Transfer Torque (STT) and Spin Orbit Torque (SOT) currents in a 512KB STT-Assisted SOT MRAM cache to its total cache area, write latency and energy consumption were investigated. The lowest cache write latencies can be achieved when the transistor widths are approximately equal. Out of all transistor sizings, the lowest write latency is 2.95ns with a corresponding cache area of 2.2756mm 2 . Meanwhile the lowest energy consumption is 441.777 pJ which is when the transistor widths are at their minimum. |
| Databáze: | OpenAIRE |
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