Fabrication of Planar-Integrated SIS Mixer Circuits with Improved Uniformity and Yield

Autor:	Yoshinori Uzawa, Wenlei Shan, Shohei Ezaki
Rok vydání:	2020
Předmět:	Fabrication Materials science business.industry Insulator (electricity) Integrated circuit Chemical vapor deposition Condensed Matter Physics 01 natural sciences Atomic and Molecular Physics and Optics 010305 fluids & plasmas law.invention Planar law Plasma-enhanced chemical vapor deposition 0103 physical sciences Ultimate tensile strength Optoelectronics General Materials Science 010306 general physics business Electronic circuit
Zdroj:	Journal of Low Temperature Physics. 199:369-375
ISSN:	1573-7357 0022-2291
DOI:	10.1007/s10909-020-02433-2
Popis:	Single-pixel prototype superconductor–insulator–superconductor (SIS) mixer integrated circuits (ICs) for multi-beam heterodyne receivers were fabricated. We introduced plasma-enhanced chemical vapor deposition (PE-CVD) for insulator layer deposition and machine-aligned via-hole etching for contact-hole definition on SIS junctions to achieve high uniformity and yield. In the PE-CVD, we applied a compressive/tensile/compressive SiO2 trilayer technique to control the film stress. The SiO2 trilayer stress was stable and negligibly low. The uniformity and junction quality yield of the single-pixel prototype SIS mixer ICs were improved in the process applying the PE-CVD and the via-hole etching.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::5b1af8e61308b5af199356a1a2bc3e74 https://doi.org/10.1007/s10909-020-02433-2 Zobrazit plný text záznamu Plný text ve formátu PDF Plný text ve formátu HTML
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