| Autor: |
Waisiu Law, W.J. Helms, David J. Allstot, Jianjun Guo |
| Rok vydání: |
2004 |
| Předmět: |
|
| Zdroj: |
IEEE Transactions on Instrumentation and Measurement. 53:1485-1492 |
| ISSN: |
0018-9456 |
| DOI: |
10.1109/tim.2004.834080 |
| Popis: |
The original digital calibration approach for 1 b/stage and 1.5 b/stage pipeline analog-digital converters produces missing or nonmonotonic digital codes with the device and circuit impairments typical of modern deep submicrometer CMOS technologies. Two digital calibration algorithms are introduced to improve pipeline performance when using low-voltage low-gain nonlinear operational amplifiers and high random dc offset voltage comparators. The first technique computes calibration coefficients for each stage at actual transition points of the residue characteristic to assure converter monotonicity in the presence of random comparator offset voltages. The second augments a conventional pipelined architecture with an input-dependent level-shifting stage and additional digital calibration circuitry to achieve high differential and integral linearity with low-gain nonlinear operational amplifiers. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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