Impact of surrounding gate transistor (SGT) for ultra-high-density LSI's
| Autor: | Katsuhiko Hieda, F. Masuoka, Kazumasa Sunouchi, Naoko Okabe, Akihiro Nitayama, Hiroshi Takato, Fumio Horiguchi |
|---|---|
| Rok vydání: | 1991 |
| Předmět: |
Engineering
business.industry Transistor Electrical engineering Hardware_PERFORMANCEANDRELIABILITY Integrated circuit Electronic Optical and Magnetic Materials law.invention Threshold voltage CMOS Hardware_GENERAL law Hardware_INTEGRATEDCIRCUITS Optoelectronics Inverter Field-effect transistor Electrical and Electronic Engineering business Hardware_LOGICDESIGN Electronic circuit Static induction transistor |
| Zdroj: | IEEE Transactions on Electron Devices. 38:573-578 |
| ISSN: | 0018-9383 |
| DOI: | 10.1109/16.75168 |
| Popis: | A transistor with compact structures for future MOS devices is discussed. This transistor, whose gate electrode surrounds the pillar silicon island, reduces the occupied area for all kinds of circuits. By using this transistor, the occupied area of the CMOS inverter can be shrunk to 50% of that using planar transistors. Other advantages, such as steep cutoff characteristics, very small substrate bias effects, and high reliability, are discussed. Its structure, which allows for the enlargement of gate-controllability to the channel and electric field relaxation at the drain edge, is described. The advantages of this SGT for large-scale integration (LSI) devices is discussed. > |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|