| Autor: |
Chien-Cheng Wei, Wu-Shiung Feng, Chia-Shih Cheng, Hsien-Chin Chiu, Shao-Wei Lin, Yong-Jhih Chen |
| Rok vydání: |
2007 |
| Předmět: |
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| Zdroj: |
PIERS Online. 3:1000-1004 |
| ISSN: |
1931-7360 |
| DOI: |
10.2529/piers060906072149 |
| Popis: |
An improved BSIM4 large-signal model for 0.13-"m gate-length high linearity CMOS RF transistors is presented in this paper. The fleld-plate technology functions the im- provements in linearity and 1/f noise of 0.13-"m CMOS devices was in our past investigation. To accurately accomplish the CMOS fleld-plate device model, an improved BSIM4 model with RLC networks representing the parasitic efiects of transmission line and lossy substrate has been adopted for microwave applications up to 40GHz. Good agreement has been realized between the measured and modeled results in terms of device's DC curves, S-parameters, 1/f noise, and power performance. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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