A 0.33-V, 500-kHz, 3.94-$\mu\hbox{W}$ 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist

Autor:	Ching-Te Chuang, Yung-Shin Kao, Ya-Ping Wu, Huan-Shun Huang, Shyh-Jye Jou, Wei Hwang, Chien-Yu Lu, Ming-Hsien Tu, Yuh-Jiun Lin, Hao-I Yang, Kuen-Di Lee
Rok vydání:	2012
Předmět:	Materials science Negative bit line business.industry Subthreshold conduction Ripple 500 kHz CMOS Redundancy (engineering) Electronic engineering Optoelectronics Static random-access memory Electrical and Electronic Engineering Performance improvement business
Zdroj:	IEEE Transactions on Circuits and Systems II: Express Briefs. 59:863-867
ISSN:	1558-3791 1549-7747
DOI:	10.1109/tcsii.2012.2231017
Popis:	This paper presents an ultra-low-power 72-Kb 9T static random-access memory (SRAM) with a ripple bit-line (RPBL) structure and negative bit-line (NBL) write-assist. The RPBL scheme provides over 40% read access performance improvement for VDD below 0.4 V compared with the conventional hierarchical bit-line structure. A variation-tolerant ripple-initiated NBL write-assist scheme with the transient negative pulse coupled only into the single selected local bit-line segment is employed to enhance the NBL, boosting efficiency and reducing power consumption. The 331 × 385 μm2 72-Kb SRAM macro has been fabricated in UMC 40-nm low-power CMOS technology and was tested with full suites of SRAM compiler qualification patterns. Error-free full functionality without redundancy is achieved from 1.5 V down to 0.33 V. The measured maximum operation frequency is 220 MHz (500 kHz) at 1.1 V (0.33 V) and 25 °C. The measured total power consumption is 3.94 μW at 0.33 V, 500 kHz, and 25 °C .
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::59c2a971d2c5d63e493c84ad8901fcee https://doi.org/10.1109/tcsii.2012.2231017 Zobrazit plný text záznamu