Gatestacks for scalable high-performance FinFETs

Autor: Ray Duffy, Gerben Doornbos, H. Roberts, Liesbeth Witters, Annelies Delabie, Andriy Hikavyy, Monja Kaiser, R.J.R. Lander, Sofie Mertens, Serge Biesemans, G. Curatola, R. G. R. Weemaes, Rita Rooyackers, Georgios Vellianitis, Stephan Beckx, Li-Shyue Lai, Malgorzata Jurczak, C. Torregiani, Frederik Leys, C. Jonville, Bartek Pawlak, F.C. Voogt, T. Vandeweyer, D. Donnet, Nadine Collaert, C. Delvaux, M.J.H. van Dal, J. Petty, Marc Demand
Rok vydání: 2007
Předmět:
Zdroj: 2007 IEEE International Electron Devices Meeting.
Popis: Excellent performance (995 muA/mum at Ioff=94 n A/mum and Vdd=lV) and short channel effect control are achieved for tall, narrow FinFETs without mobility enhancement. Near-ideal fin/gate profiles are achieved with standard 193 nm immersion lithography and dry etch. PVD TiN electrodes on Hf SiO dielectrics are shown to give improved NMOS performance over PEALD TiN whilst poorer conformality, for both dielectric and gate electrode, does not appear to impact scalability or performance. Excellent PMOS performance is achieved for both PEALD and PVD TiN. A new model for threshold voltage VT variability is shown to explain this dependence upon fin width and gate length.
Databáze: OpenAIRE