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This work intends to overcome the issues encountered in the use of commercial EDA tools to design fault-tolerant circuits based on the Triple Modular Redundancy (TMR) technique. Circuit optimizations performed by the tool tend to remove the added redundant logic or induce to apply further constraints that lead to non optimal fault-tolerant designs. Thus, this work proposes an approach to automate the implementation, optimization, and verification of TMR circuits in commercial technologies. Three steps are added to the front-end design of ASICs. First, employing a post-synthesis netlist and according to the desired granularity level the TMR technique is applied, three different TMR versions of the circuit can be implemented automatically. Afterwards, gate sizing is performed over the resulting circuit in order to improve performance. Third, equivalence checking is used to verify both correct functionality and fault-tolerant capability of the TMR circuit with regards to the original circuit. The proposed approach is employed on a set of architectures of a case-study circuit. Results show the area and performance overhead for the different TMR implementations and the efficiency of the verification process with different logic optimization and performance optimizations. |
