A fully scaled 0.5μm CMOS process for fast random logic
| Autor: | M. Guerin, M. Lerme, Simon Deleonibus, F. Vinet, C. Jaffard, G. Reimbold, G. Guegan, C. Leroux, M. Belleville, M. Heitzmann, François Martin |
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| Rok vydání: | 1991 |
| Předmět: |
Materials science
business.industry Dielectric Condensed Matter Physics Atomic and Molecular Physics and Optics Surfaces Coatings and Films Electronic Optical and Magnetic Materials law.invention Power (physics) CMOS law Optoelectronics Static random-access memory Electrical and Electronic Engineering Spark plug business Random logic Access time Electronic circuit |
| Zdroj: | Microelectronic Engineering. 15:257-260 |
| ISSN: | 0167-9317 |
| DOI: | 10.1016/0167-9317(91)90224-2 |
| Popis: | An advanced high performance 0.5 μm technology for fast CMOS circuits has been developed. The main features for this 0.5 μm technology include : diffused wells, field isolation with a SILO/RTN process, N+ polysilicon gate, TaSi2 gate material, contact with W plug, RTA for both BPSG reflow and junction activation, double aluminum metallization levels using BSG-sacrificial SOG-BSG as intermetal dielectric. These modules allow 0.5 μm design rules. Ring oscillators delay time of 72 ps, 6ns access time for a 16k × 1 SRAM and a typical 16×16-bit multiplication time of 7.5 ns were measured at a power supply of 3.3 V. |
| Databáze: | OpenAIRE |
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