A three-dimensional high-throughput architecture using through-wafer optical interconnect
| Autor: | S.T. Wilkinson, W.S. Lacy, Myunghee Lee, C. Camperi-Ginestet, Nan Marie Jokerst, Martin A. Brooke, B. Buchanan, D.S. Wills, H.H. Cat |
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| Rok vydání: | 1995 |
| Předmět: |
Digital electronics
Interconnection Computer science business.industry Optical interconnect Electrical engineering Optical computing Integrated circuit Atomic and Molecular Physics and Optics law.invention Computer Science::Hardware Architecture Computer Science::Emerging Technologies law Hardware_INTEGRATEDCIRCUITS Electronic engineering Wafer business Microfabrication Electronic circuit |
| Zdroj: | Journal of Lightwave Technology. 13:1085-1092 |
| ISSN: | 0733-8724 |
| DOI: | 10.1109/50.390224 |
| Popis: | This paper presents a three-dimensional, highly parallel, optically interconnected system to process high-throughput stream data such as images. The vertical optical interconnections are realized using. Integrated optoelectronic devices operating at wavelengths to which silicon is transparent. These through-wafer optical signals are used to vertically optically interconnect stacked silicon circuits. The thin film optoelectronic devices are bonded directly to the stacked layers of silicon circuitry to realize self-contained vertical optical interconnections. Each integrated circuit layer contains analog interface circuitry, namely, detector amplifier and emitter driver circuitry, and digital circuitry for the network and/or processor, all of which are fabricated using a standard silicon integrated circuit foundry. These silicon circuits are post processed to integrate the thin film optoelectronics using standard, low cost, high yield microfabrication techniques. The three-dimensionally integrated architectures described herein are a network and a processor. The network has been designed to meet off-chip I/O using a new offset cube topology coupled with naming and renting schemes. The performance of this network is comparable to that of a three-dimensional mesh. The processing architecture has been defined to minimize overhead for basic parallel operations. The system goal for this research is to develop an integrated processing node for high-throughput, low-memory applications. > |
| Databáze: | OpenAIRE |
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