Process development of a maskless N40 via level for security application with multi-beam lithography
| Autor: | Philippe Essomba, Gerard ten Berge, Marco Jan-Jaco Wieland, Philippe Brun, Jonathan Pradelles, Stefan Landis, Yoann Blancquaert, Patricia Pimenta-Barros, Isabelle Servin, Arthur Bernadac, Allan Germain |
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| Rok vydání: | 2018 |
| Předmět: |
010302 applied physics
Materials science business.industry Copper interconnect 02 engineering and technology Overlay 021001 nanoscience & nanotechnology 01 natural sciences CMOS Stack (abstract data type) 0103 physical sciences Optoelectronics Wafer 0210 nano-technology business Lithography Massively parallel Electron-beam lithography |
| Zdroj: | Novel Patterning Technologies 2018. |
| DOI: | 10.1117/12.2297162 |
| Popis: | The maskless electron beam lithography system, based on massively parallel electron-beam writing strategy has the ability for low-cost production of truly unique individual chips in volume manufacturing, compatible with optical systems. Mapper Lithography has introduced the FLX-1200 platform installed at CEA-Leti. This paper will present fully process-integration stepwise developments to be compliant with the single via layer demanding targets based on dual damascene process: The lithographic performances and etch transfer optimization were firstly evaluated on a layer stack representative of N40 CMOS technology by developing step-by-step approach: - 1/ Trilayer lithography of via layer and partial etch into low-k development with VSB 50kV - 2/ Litho/etch process of product wafer with VSB 50keV - 3/ Trilayer lithography of via pattern and etch into low-k for FLX-1200 multi-beam 5kV - 4/ last litho of via pattern on product wafer using FLX (no etch yet). In addition, the overlay and CDU capability of FLX-1200 are assessed for via 3, and the alignment to product wafer is tested. Via patterning integration showing the up-to-date achievements is mature enough to start first customer demos for security application. |
| Databáze: | OpenAIRE |
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