| Autor: |
Jamal Qureshi, Roger Quon, Raymond Caramto, Daniel N. Pascual, Sitaram Arkalgud, Larry Smith, Robert Edgeworth, Stephen Olson, Klaus Hummler, Andy Rudack |
| Rok vydání: |
2011 |
| Předmět: |
|
| Zdroj: |
2011 IEEE/SEMI Advanced Semiconductor Manufacturing Conference. |
| DOI: |
10.1109/asmc.2011.5898174 |
| Popis: |
Three-dimensional (3D) die stacking using through silicon viae (TSV) promises significant improvements in performance, power consumption and size over traditional edge-connected die stacking (e.g. wire bonds) or package-on-package (PoP) based approaches. 3D integrated circuits (3D-IC) using TSV will enable new system in package (SiP) applications, especially where ultra-high memory bandwidth at moderate power consumption is needed. This paper describes the technology elements for a successful implementation of TSV in high volume manufacturing (HVM) with special focus on the so-called “TSV mid” integration flow being developed at SEMATECH. The maturity and readiness of each process module for HVM is assessed. In addition to technological feasibility and manufacturing readiness, 3D-IC adoption requires an environment of agreed upon specifications, standards, and tools (3D ecosystem). Progress toward a well defined 3D ecosystem by SEMATECH and many other organizations is described in part III of this paper. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
|
